This invention relates to a display control apparatus and, more particularly, to a display control apparatus for presenting a display by generating a signal having a divided frequency on the basis of the frequency of a reference signal.
A well-known example of a circuit which, on the basis of the frequency of a given reference signal, generates a signal whose frequency is a frequency-divided of the reference frequency is an oscillator circuit referred to as a PLL (phase-locked loop) which compares the reference signal and the output signal in terms of both frequency and phase and performs control in such a manner that the input signal and a frequency signal outputted by a VCO (voltage-controlled oscillator) maintain a phase difference that is proportional to the difference between the free oscillation frequency of the VCO and the frequency of the input signal. In a PLL circuit of this kind, the output signal from the VCO is frequency-divided by a prescribed dividing value (a preset value), after which the frequency and phase of the resulting signal are compared with the frequency and phase of the reference signal. For example, in a display apparatus, a horizontal synchronizing signal is adopted as the reference signal and a PLL circuit of the above-mentioned type is used to multiply the frequency of the reference signal and generate the synchronizing clock of a video signal.
However, there are display apparatus in which the horizontal synchronizing signal serving as the reference signal is outputted at a frequency different from that at the time of the display operation in intervals where a vertical synchronizing signal is off, by way of example. In case of such an apparatus, the fact that the conventional PLL circuit can be preset to only one dividing value means that the PLL circuit will not operate normally during the time that the vertical synchronizing signal is off. The result is an increase in jitter or failure of the PLL circuit to lock the output signal.